PCIe Gen7 is Here!

On June 11, 2025, PCI-SIG launched PCIe Version 7.0!  The specification is available for download by PCI-SIG members.

PCI-SIG has taken a "tick-tock" approach as of late:  a cycle of major electrical change followed by a refinement of that change.  For example, PCIe Gen4 was a major electrical change, refined in PCIe Gen5; PCIe Gen6 was a major change, for example switching from 128b/130b encoding to PAM4/FLIT, and PCIe Gen7 is a refinement to that change.  However, no matter how you describe the change, PCI-SIG continues its 20+ year tradition of doubling the bandwidth every generation!

Here is a description of some of the design goals of PCIe Gen7:

The improvements came from a variety of sources, for example:

• reducing reference clock jitter
• doubling the Nyquist frequency
• accepting a higher bit error rate (BER) than previous generations
• requiring less signal loss from PCBs and CEM connectors
• ...and other such electrical improvements

PCI-SIG hosted a webinar to formerly announce the new specification and outline the high-level benefits and technical improvements delivered by PCIe Gen7:

Hello PCI-SIG members,

Interested in learning more about the technical features of the PCI Express specification? Register today for the upcoming PCI-SIG webinar “PCIe 7.0 Specification: Next-Generation Performance to Meet the Needs of Advanced AI Applications” on Tuesday, July 15 at 9:00 – 10:00 a.m. PT. PCIe technology experts will discuss the motivations behind the PCIe 7.0 specification and will provide a first look at the innovative features that enable the PCIe 7.0 specification to reach 128.0 GT/s raw data rate, and up to 512 GB/s bi-directionally via a x16 configuration.

About the Webinar

The PCIe 7.0 specification is the latest generation of PCIe technology, which has served as the de facto high-bandwidth interconnect of choice for over two decades. This technical webinar will explore the motivations behind the PCIe 7.0 specification – driven by the industry demand for a high-performance, scalable IO interconnect – and how PCI-SIG achieved doubling the bandwidth of the PCIe 6.0 specification (64.0 GT/s) in three years. Attendees will learn how the PCIe 7.0 specification meets the evolving bandwidth needs of advanced AI applications in data-intensive markets like Hyperscale Data Centers, HPC (High Performance Computing), Automotive and Military/Aerospace. 

PCIe technology experts will discuss the innovative features that enable the PCIe 7.0 specification to reach 128.0 GT/s raw data rate, such as PAM4 (Pulse Amplitude Modulation with 4 levels) signaling, improved power efficiency, and backwards compatibility with previous generations of PCIe technology. 

Presenters:

• Debendra Das Sharma (Intel)
• Mohuiddin Mazumder (Intel)

This presentation is now available at no charge, on-demand, on BrightTALK:  https://www.brighttalk.com/webcast/17656/645778

PCI-SIG's commitment to doubling bandwidth every three years is matched by their commitment to maintaining backwards compatibility from a BIOS/FW/SW perspective.  The changes required by PCIe Gen7 are electromechanical in nature, and won't break the FW/SW abstractions we use today.

It will be many years before PCIe Gen7 becomes commonplace in the industry.  The major silicon suppliers don't even have PCIe Gen6 hardware shipping today, much less PCIe Gen7.  However, as always, the first step is getting the industry to agree on a standard, and that's what we've done here with PCIe Gen7.  Looking forward to the performance improvements ahead!