On June 21, 2022, the DMTF released SMBIOS Spec version 3.6.0.

The new SMBIOS Spec is available for download here:

Brief Background

Recall that the SMBIOS specification defines data structures, and associated access methods, that can be used by the BIOS to publish system management information for consumption by other software, most notably the operating system.  This eliminates the need for the operating system to probe hardware directly to discover what devices are present in the computer. The SMBIOS specification is produced by the Distributed Management Task Force (DMTF) and has been the standard management information format since 1995.

New in v3.6.0

Here's a brief summary of the change requests (CR) that went into v3.6.0:
  • Processor Information (Type 4):
    • SMBIOSCR00214: Added new processor sockets
    • SMBIOSCR00215: Added processor family ID for ARMv9
    • SMBIOSCR00218: Added new processor socket types
    • SMBIOSCR00219: Added “thread enabled” field
  • Memory Device (Type 17):
    • SMBIOSCR00220: Added HBM3
  • Various:
    • SMBIOSCR00217: Added LoongArch processor architecture
Following are the changes in more detail:

SMBIOSCR00214: Added new processor sockets

This CR added three new socket types to the Type 4 Processor Information table to represent CPU products made by Intel.  Specifically, the Processor Information — Processor Upgrade field was updated.

SMBIOSCR00215: Added processor family ID for ARMv9

ARM has a new processor family called ARMv9.  This CR added ARMv9 to the Type 4 – Processor Information table, in the Processor Family field:

SMBIOSCR00218: Added new processor socket types

This CR added two new socket types to the Type 4 Processor Information table to represent CPU products made by Alibaba Inc.  Specifically, the Processor Information — Processor Upgrade field was updated.

SMBIOSCR00219: Added “thread enabled” field

This CR was requested by Intel, and its purpose is to add a new field, "Thread Enabled", to distinguish between number of threads supported by the CPU hardware versus number of threads the BIOS has enabled.  The Type 4 table has long had fields to represent the number of CPU threads:  Thread Count and Thread Count 2.  However, there is ambiguity regarding whether those are meant to represent the threads supported in the CPU hardware?  Or how many threads BIOS has enabled, assuming the BIOS gives the user the ability to disable some number of threads.  Adding Thread Enabled to represent the number of threads enabled by BIOS makes the distinction clear.

SMBIOSCR00220: Added HBM3

This CR was requested by AMD with the goal of adding the High Bandwidth Memory Generation 3 (HBM3) memory type to the Memory Device (Type 17) table.

SMBIOSCR00217: Added LoongArch processor architecture

LoongArch is a new processor Instruction Set Architecture (ISA) developed by the Loongson Technology company.  LoongArch is a RISC-style ISA descended from MIPS, and shares some similarity with RISC-V.

LoongArch changes were made throughout the specification in those tables wherever CPU information is described.
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